Public info about the author: Federico

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SPICE simulation enthusiast

  • SPICE simulation of a Flip flop D implemented with two latch synchronous to solve the problem of “transparency”.

    • For-Credits
    • Intermediate
    • 11-20
    • PSpice
    • 9.1+
    • No
    • flip flop D with 2latch master slave simulation

  • PSpice simulation of a 24 Bit comparator implemented with 4 Bit Comparators.

    • For-Credits
    • Intermediate
    • <10
    • PSpice
    • 9.1+
    • No
    • 24 bit comparator simulation

  • SPICE simulation of a 4 bit shift register Parallel Input Parallel Output implemented with D flip flop.

    • For-Credits
    • Intermediate
    • PSpice
    • 9.1+
    • No
    • 4 bit PIPO shift register with flip flop D output simulation

  • SPICE simulation of a Serial Input Serial Output shift register implemented with flip flop D.

    • Free
    • Simple
    • <10
    • PSpice
    • 9.1+
    • No
    • shift register siso simulation

  • SPICE simulation of JK flip flop implemented with a D flip flop, it solves the drawback of indetermination when both J and K are 1.

    • Free
    • Simple
    • <10
    • PSpice
    • 9.1+
    • No
    • jk flip flop by a D flip flop simulation