D level-sensitive Latch in CMOS IC

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SPICE simulation with LTspice of a D latch implemented with two cross-coupled CMOS inverters. When the clock signal is high, the output “follows” the input with a delay, When the clock goes low, the value of output Q cannot change until the clock goes back high again.

  • Free
  • Simple
  • 11-20
  • LTspice
  • IV
  • No
  • time analysis of D level-sensitive latch Q output (green) D input (blue) C clock (red) output changes with high clock level

1 review for D level-sensitive Latch in CMOS IC

  1. muhaned84

    thank you for help us with this circuit

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