input NRZ data is analternating string of ones and zeros
input NRZ data is a string of seven zeroes followed by a single one
voltage controlled delay line
Hogge phase detector

DPLL circuit for 1 Gbit/s clock recovery

0 Credits

2042a32d-e691-411a-b7c8-b2ae425860b1.zip

Login for download
Category:

Description

SPICE simulation of 1 Gbit/s clock recovery circuit using a NRZ (Non Return to Zero) data format. The Digital Phase Locked Loops used for clock recovery uses a Hogge phase detector and a VCDL (Voltage Controlled Delay Line), the output of which is fed back to get a positive feedback for sustaining the oscillation.

  • Free
  • Advanced
  • >100
  • LTspice
  • IV
  • No
  • input NRZ data is analternating string of ones and zeros input NRZ data is a string of seven zeroes followed by a single one voltage controlled delay line Hogge phase detector

Reviews

There are no reviews yet.

Only logged in customers who have purchased this product may leave a review.

Related products