Edge triggered D Flip Flop

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SPICE simulation of an edge triggered D flip flop implemented with two level-sensitive latches in cascade. When the clock goes high, the output “follows” the input. The value of output Q can’t change its state until next rising front of clock.

  • Free
  • Intermediate
  • 11-20
  • LTspice
  • IV
  • No
  • time analysis of D flip flop Q output (red) follows D input (green) on rising front of clock (blue)

1 review for Edge triggered D Flip Flop

  1. asasfaf

    you can not make CMOS d flip flop on Spice without going to internet and finding out this circuit. very helpful.

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