time analysis
D latch and enhanced D latch transient comparation

Enhanced CMOS D level-sensitive Latch

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Description

LTspice simulation of a D that latch uses two transmission gate and requires an additional clock signal.It improves the noise perfomance and reduces the output delay.

  • Free
  • Intermediate
  • 11-20
  • LTspice
  • IV
  • No
  • time analysis D latch and enhanced D latch transient comparation

1 review for Enhanced CMOS D level-sensitive Latch

  1. faith2012 –

    thank you

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