Parallel In Serial Out Shift register

Description

the circuit is implemented with D flip-flops and nand gates. D0, D1, D2 and D3 are the parallel inputs, where D0 is the most significant bit and D3 is the least significant bit. when the shift/write line is low, the data is written, when the line is high, the data is shifted. The register performs right shift operation on the application of a clock pulse.

• Project Type: Free
• Complexity: Simple
• Components number: 11-20
• SPICE software: PSpice
• Software version: 16.5+
• Full software version nedeed : No
• Screenshots simulation images: