Half Bridge Simulation with State Machine Model

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This SPICE simulation is performed with a state machine model, used to replace complex sets of circuitry. The block is described by an ASCII txt state file, where the first column defines the state, the second column defines the output for the state, the third column defines the expected input and the fourth column defines the state to transition to if the input is present during the positive edge of the clock signal. The state file of this circuit defines 128 states.

  • Free
  • Intermediate
  • 11-20
  • ICAP/4
  • 8.1.6+
  • Yes
  • Transient analysis overview State machine model State file


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