D level-sensitive Latch in CMOS IC
time analysis of D level-sensitive latch
Q output (green) D input (blue) C clock (red) output changes with high clock level
  1. D level-sensitive Latch in CMOS IC
  2. time analysis of D level-sensitive latch
  3. Q output (green) D input (blue) C clock (red) output changes with high clock level

D level-sensitive Latch in CMOS IC

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Description

SPICE simulation with LTspice of a D latch implemented with two cross-coupled CMOS inverters. When the clock signal is high, the output “follows” the input with a delay, When the clock goes low, the value of output Q cannot change until the clock goes back high again.

  • Free
  • Simple
  • 11-20
  • LTspice
  • IV
  • No
  • time analysis of D level-sensitive latch Q output (green) D input (blue) C clock (red) output changes with high clock level

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