8 stage Voltage-Controlled Delay Line

Description

SPICE simulation of an 8 stage voltage controlled delay line. The VCDL is used to provide delay in a delay locked loop (DLL). This schematic has eight delay cells. The differential inputs were generated using an inverter and a transmission gate. The outputs are evenly spaced and they only swing up to Vref = 500mV. This is done to minimize the effects of power supply and ground noise on the delay of the circuit.

• Project Type: Free
• Complexity: Advanced
• Components number: 51-100
• SPICE software: LTspice
• Software version: IV
• Full software version nedeed : No
• Screenshots simulation images: