DPLL Digital Phase Locked Loops with XOR Phase Detector

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SPICE simulation of a DPLL with XOR phase detector. This is a fundamental circuit in the transmission of digital data. Before the transmission, data is loaded into a shift register and shifted out sequentially, using a system clock. At the receiving side, the receiver amplifies and eventually change the data back into digital logic levels. To shift the data back into a shift register, a clock signal is necessary. The DPLL generates a clock signal locked with the incoming signal, and clocks the shift register for recovering transmitted data.

  • Free
  • Advanced
  • >100
  • LTspice
  • IV
  • No
  • ideal input data (green) string of alternating ones and zeroes sequence of a one followed by seven zeroes the rising edge of the clock has a little offset called static phase error XOR phase detector VCO divide by 2 circuit


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