are you refering to the A3 AND gate in both projects? The purpose of this AND gate is to reset the D flipflop when both of them have their Q output set to 1. And then to prevent from having the state where QB=QH=1. This topology is found in the litterature (projet.asc) and works on ORCAD PSPICE.
You’re right, I thought you were referring to the AND gate as tristate. I’ve found in the site this Phase frequency detector by Jacob Baker to which I added a CMOS tri state.hope it’s useful for you. About the configuration with the AND gate can you give me a reference?
By the way, I can’t open the PSpice file, what version is it?