LTspice Modeling of Universal Operational Amplifier

LTspice model with 4 levels of accuracy of the description of an operational amplifier.The first level models a linear single pole opamp with no slew rate or output voltage range limit. The second level introduces the slew rate and output voltage and current limit. The third level is a two pole with programable phase margin […]

Low Noise Preamplifier for Satellite Base Station

LTspice Bias circuit simulation and PCB Eagle file of a low noise amplifier circuit (LNA ) for satellite. 3 different bias networks are compared in this simulation. Project Type: Free Complexity: Intermediate Components number: 11-20 SPICE software: LTspice Software version: IV Full software version nedeed : No Screenshots simulation images:

Using a Stepped PWL input file

Using a PWL file to input a waveform into a circuit is simple. But if you have to step through several waverform files, it becomes difficult to implement. This method allows LTSpice to step through each waveform input file so that the results of your simulation can be compared on the graph. Project Type: Free […]

Marshall Leach Low IMD Amplifier

LTspice simulation of the last version of low transient intermodulation distortion amplifier by Professor W. Marshall Leach. The amplifier is a fully complementary, direct-coupled design, with a closed loop frequency response wich extends from 0.5hz to above 200khz. Project Type: Free Complexity: Advanced Components number: 51-100 SPICE software: LTspice Software version: IV Full software version […]

Enhanced CMOS D level-sensitive Latch

LTspice simulation of a D that latch uses two transmission gate and requires an additional clock signal.It improves the noise perfomance and reduces the output delay. Project Type: Free Complexity: Intermediate Components number: 11-20 SPICE software: LTspice Software version: IV Full software version nedeed : No Screenshots simulation images:

D level-sensitive Latch in CMOS IC

SPICE simulation with LTspice of a D latch implemented with two cross-coupled CMOS inverters. When the clock signal is high, the output “follows” the input with a delay, When the clock goes low, the value of output Q cannot change until the clock goes back high again. Project Type: Free Complexity: Simple Components number: 11-20 […]

Switching delays in a 3 input CMOS NAND

LTspice Parametric analysis of switching delays in a 3 input Nand gate with a load capacitance that varies from 0 to 100 femtoFarad. Project Type: Free Complexity: Simple Components number: <10 SPICE software: LTspice Software version: IV Full software version nedeed : No Screenshots simulation images:

3 inputs NOR gate with CMOS

LTspice simulation of a NOR static logic gate with 3 parallel NMOS and 3 series PMOS. The voltage switching point of NOR gate has a low value than ideal value of 2.5 Volt. Project Type: Free Complexity: Intermediate Components number: <10 SPICE software: LTspice Software version: IV Full software version nedeed : No Screenshots simulation […]

3 inputs NAND gate with CMOS

LTspice siulation of a NAND static logic gate with 3 parallel PMOS and 3 series NMOS. Analysis of voltage transfer curve. Project Type: Free Complexity: Intermediate Components number: <10 SPICE software: LTspice Software version: IV Full software version nedeed : No Screenshots simulation images:

Astable multivibrator with CD4011

SPICE simulation with LTspice of an Astable multivibrator with CD4011. Project Type: Free Complexity: Very simple Components number: <10 SPICE software: LTspice Software version: IV Full software version nedeed : No Screenshots simulation images: