Quick Solutions to Solve SPICE Convergence Issues.

This article delves into the critical subject of to Solve SPICE Convergence Issues. The solutions presented for addressing convergence issues are of a general nature and are applicable across various algorithms, such as PSPice, XSPICE, NGSPICE, IsSPICE, and HSPICE. By understanding and effectively managing convergence challenges in SPICE simulations can enhance the reliability and accuracy of their electronic circuit analyses, regardless of the specific SPICE variant they are utilizing.

Convergence problems in SPICE simulations primarily manifest in three distinct categories:

Circuit Topology Errors

The SPICE simulation software frequently signals these types of errors with precise messages, rendering their identification and rectification relatively straightforward.

SPICE simulator Options Settings

For instance, during transient analysis, selecting an appropriate timestep corresponding to the device’s operational frequency becomes very important. At times, a compromise between accuracy and convergence stability is required; as accuracy is increased, the likelihood of encountering convergence errors also rises.

Unrealistic SPICE models

Convergence problems can stem from SPICE models characterized by significant nonlinearities and discontinuities. Such models introduce complexities that can challenge the simulation’s convergence process.

Now, let’s delve into the strategies that swiftly address the most prevalent convergence challenges arising from these distinct problem categories in order to effectively solve SPICE convergence issues.

Circuit Topology Errors

Ground Absence, Error Message: Node is Floating.

The SPICE algorithm computes voltage for every circuit point relative to a reference point—this reference point is specifically the ground, an essential component in the circuit. Including the ground reference wherever needed suffices to address this issue.

Lack of Direct DC Ground Path, Error Message: Node is Floating.

Building on the insights from the prior scenario, it’s essential to verify the absence of circuit points isolated from the ground reference. If an apparent isolation is intended for a node from the ground, this can be achieved by introducing a high-value resistor that ensures continuity with the ground reference. Ensure that the node maintains a direct connection with the ground reference.

Unmodeled pins, error message: Less than two connections at node

This error emerges when the Capture component lacks an associated SPICE model or when a wire is “floating,” connected to a device pin without a corresponding connection to another pin.

Prevent Loops Involving Voltage Sources or Inductors, Error Message: Voltage Source or Inductor Loop

A potential solution involves incorporating a minor series resistance.

Avoid series capacitors or current sources

Ensure the absence of series capacitors or series current sources.

Convergence Problems due to SPICE Simulation options settings

Primarily, it’s crucial to establish a suitable timestep corresponding to the device being simulated. For instance, if we intend to simulate a 1 kHz oscillator with a period of T=1 ms, it’s advisable to configure a timestep on the order of T/10 or even lower. This ensures a satisfactory simulation resolution.

Let’s categorize the solutions applicable to the two principal types of analysis: DC and Transient. Notably, once DC convergence is achieved, the AC analysis will also converge.

Solve SPICE convergence issues for DC Analysis

ITL1: set ITL1=500, this set iterations limit that SPICE will perform for DC and bias.

ITL2: set ITL2=500, this set iterations limit that SPICE will perform for DC and bias before giving up.

ITL6: set ITL6=100 (Advanced Options), this increases Source stepping iteration limit, Default value
is 0, which disables source stepping.

Reduce ABSTOL Absolute current tolerance, it should be set to about 8 orders of magnitude below the level of maximum current, the dafault value is 1pA

Diminish VNTOL Absolute voltage tolerance, as for ABSTOL it should be set to about 8 orders of magnitude below the level of maximum voltage, the default value is 1uV

Modify RELTOL this is the relative error allowed for node voltage and branch current. Set RELTOL= 0.01 to reach a compromise between accuracy and simulation run time. The default value is 0.001.

GMIN set GMIN = 1n or 0,1n. GMIN is the minimum conductance across all semiconductor devices

GMINSTEPS (Advanced Options) set GMINSTEPS=200 . This option adjusts the number of increments for GMIN during the DC analysis.

Change DC Power supplies into Pulse generator

NODESETs use .NODESETs statement to assign a voltage to a node. This can be done for example when the node-voltage table shows unrealistic voltages. If it’s not available a proper estimation of the node DC voltage, use a .NODESET of 0V.

Solve SPICE convergence issues for Transient Analysis

RELTOL also for the transient analysis Set RELTOL= 0.01 (The default value is 0.001), that decreases the accuracy
of the simulation by increasing the error tolerance required for convergence.

ITL4 set ITL4=2000 , this increases the number of iterations before a nonconvergence warning is issued

reduce ABSTOL Absolute current tolerance, it should be set to about 8 orders of magnitude below the level of maximum current, the dafault value is 1pA

Reduce VNTOL Absolute voltage tolerance, as for ABSTOL it should be set to about 8 orders of magnitude below the level of maximum voltage, the default value is 1uV

ITL5 set ITL5=0 that assigns infinity to the total transient iteration limit.

Reduce rise and fall of PULSE sources

GEAR (Advanced Options) Select METHOD=GEAR, this is the integration method that SPICE uses to solve transient equations. Very useful for oscillators and switching circuits SPICE simulations.

TRTOL set TRTOL=40. this is the tolerance for integration error calculated using transient analysis. The TRTOL
value should NOT be greater than 1/RELTOL. the default value is 7.

IC set Initial conditions for the capacitors at their expected operating voltage. Setting this data causes
SPICE to bypass the DC operating point analysis.

Utilize Reliable SPICE Models.

It’s essential to acknowledge that SPICE models do not perfectly mirror the devices they represent; rather, they offer a partial depiction. SPICE models featuring pronounced non-linearities or abrupt discontinuities have the potential to trigger substantial convergence difficulties.

These abrupt shifts might stem from the exclusion of certain device behaviors, such as parasitic elements like capacitance across all semiconductor junctions, stray capacitance, and RC snubbers encircling diodes. In most instances, it’s advisable to rely on vendor-released SPICE models. However, if directly modeling the device, it becomes imperative to diligently mitigate any sources of discontinuities and non-linearities to ensure smoother operation.

SPICE Simulation Libraries:

On this page, you can find libraries of SPICE models for various components, released by major electronic device manufacturers.

Reference:

EMA Design Automation Resolving Simulation Errors
SPICE Circuit Handbook Steven. M Sandler Charles Hymowitz

Circuit Breaker SPICE Simulation.

Experience precise Circuit Breaker SPICE Simulation with an advanced electrical model. Accurately replicate behavior across overcurrents, including the magnetic region. Validated against real-world tests, enhance protection performance in telecom DC systems.

T. ROBBINS
TELSTRA RESEARCH LABORATORIES
BOX 249 ROSEBANK MDC, CLAYTON VICTORIA 3168, AUSTRALIA
Email: t.robbins@trl.oz.au

Abstract: This article describes an electrical model of a thermalmagnetic circuit-breaker that can accurately simulate characteristic behaviour over a wide range of overcurrents, including operation in the magnetic region. The model has been validated against measured waveforms from both a high-current DC test facility and a distributed power system rack. The circuit-breaker model can be coupled with other distribution component models to simulate the protection performance in telecommunications DC distribution systems.

1.Introduction

The performance of protection, distribution and storage devices significantly affects both the reliability and safety of the DC power system. Voltage excursions caused by an over-current instance can cause electronic equipment to malfunction due to over-voltage, and disrupt service due to under-voltage. Poor discrimination between protection devices can cause upstream device operation, resulting in major interruption to service. The rapid advancement of both computing power and analogue circuit simulation programs derived from SPICE software provides a relatively user-friendly environment for over-current protection design and analysis. This is advantageous as telecommunications power distribution systems are often large and complex, and developing an equivalent circuit model for a power system is not a trivial task.

The circuit-breaker model described in this article implements the enhanced modelling functions available with PSpice’s Analog Behavioural Modelling to include circuit-breaker current, time and arcing dependent characteristics. This model complements and extends previously published modelling work [1-2] by Telstra Research Laboratories on other power system components.

2.Circuit-Breaker Characteristic Operation

A typical thermal-magnetic circuit-breaker operates (trips) in two distinct modes; the thermal mode occurs for device currents from 1 up to about 10-15 times the rated setting current, and the magnetic mode occurs for all current levels above the thermal operating region. Characteristic current-time curves for the device operating in the thermal region can be approximated by an equation where i n t equals a constant, whereas in the magnetic region the operating time (typically <20ms) is not well defined in device data curves and specifications, as test circuits are based on rectified AC power sources which have typical rise times exceeding a few milliseconds.

The circuit-breaker model presented in this paper has been developed for a 125A moulded device (10kA fault rating), which is commonly used to protect individual battery strings within Telstra’s distributed power supplies.

For device operation in the thermal region, the characteristic i n t form of the current-time curve can be obtained from the device specification curve as shown in Figure 1. A value of n = 3.5 gives an adequate fit over the range of currents within the thermal operating region.

Fig.1 125A circuit-breaker current-time operating boundary curves (courtesy of GEC ALSTHOM AUSTRALIA). — Fig.1 125A circuit-breaker current-time operating
boundary curves (courtesy of GEC ALSTHOM
AUSTRALIA).

For device operation in the magnetic region, characteristic current-arc voltage-time behaviour has been observed for the circuit-breakers operating in a high-current DC test facility over a range of current levels and circuit time constants. At the start of such a fault instance, the current passing through the closed circuit-breaker contacts increases to a level where magnetic activation forces the contacts to open. As the contacts start to open an arc is developed which is inherently unstable and a complex voltage-current characteristic occurs as the arc progresses through to extinction.
For the 125A circuit-breaker operating in the magnetic region, the contacts are forced open when the current level typically rises above 2-4kA. Circuit-breaker operation was measured over a range of circuit conditions, such as:

· fast rates of current rise exceeding 10kA/ms, which resulted in short pre-arcing times of about 0.15- 0.2ms (eg. results from a test circuit with 5.4kA prospective current and 0.26ms time constant are shown in Figure 2).

· high prospective current levels exceeding 10kA, which result in pre-arcing times around 0.9ms for circuit time constants of about 1.2ms, as shown in Figure 3. It should be noted that special oscilloscope probing and current shunt techniques are required to record clean waveforms in the high transient noise environment that occurs in a high current test facility.

Fig.2 Measured current and voltage waveforms for a 125A circuit-breaker operating in 54VDC test circuit with 5.2kA prospective current and 0.25ms prospective time constant; 1kA/div current, 20V/div voltage and 0.5ms/div. — Fig.2 Measured current and voltage waveforms for
a 125A circuit-breaker operating in 54VDC test circuit
with 5.2kA prospective current and 0.25ms prospective
time constant; 1kA/div current, 20V/div voltage and
0.5ms/div.

Fig. 3 Measured current and voltage waveforms for a 125A circuit-breaker operating in 54VDC test circuit with about 12kA prospective current and about 1ms prospective time constant; 1kA/div current, 50V/div voltage and 0.5ms/div. — Fig. 3 Measured current and voltage waveforms for
a 125A circuit-breaker operating in 54VDC test circuit
with about 12kA prospective current and about 1ms
prospective time constant; 1kA/div current, 50V/div
voltage and 0.5ms/div.

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Fuse Model SPICE Simulation.

Fuse Model SPICE Simulation. The creation of a precise fuse model within SPICE-derived software. Discover how this model accurately captures characteristic fuse parameters and can even be tailored to simulate circuit breaker operations. Streamline your over-current protection design for telecommunication DC power systems with cutting-edge simulation tools.

T. Robbins
Telecom Australia Research Laboratories
770 Blackburn Road, Clayton, 3168
Australia

Abstract: The design and analysis of over-current protection for telecommunication DC power systems can be greatly assisted by the use of a computer-aided simulation tool. This article reports on the development of a fuse model for SPICE derived software that can accurately represent characteristic fuse parameters. The fuse model can also be adapted to represent the operation of circuit breakers.

1.Introduction

The design and analysis of over-current protection for telecommunication DC power systems can be greatly assisted by the use of a computer-aided simulation tool. However, a simulation is only as accurate as the component models and element values used to represent the real world. This article reports on the development of a fuse model that can accurately represent fuse characteristics. The fuse model can also be adapted to represent the operation of circuit breakers.
The performance of over-current protection devices significantly affects both the reliability and safety of the DC power system. Voltage excursions resulting from the operation of a fuse during a short circuit can cause electronic equipment malfunction due to over-voltage, and disrupt service due to under-voltage. Poor discrimination between protection devices can cause upstream device operation, resulting in major interruption to service.

The rapid advancement of both computing power and analogue circuit simulation programs derived from SPICE software provide a user-friendly environment for over-current protection design and analysis. This environment is advantageous as telecommunications power distribution systems are often large and complex, and developing an equivalent circuit model for apower system is not a trivial task.

The analysis of DC distribution systems using computer simulation has been shown to provide fair agreement between simulated and experimental results [1,2,3]. However, the fuse models developed have not been able to accurately represent fuse characteristics. Typical parameters for a fuse operating in a circuit with a given time constant and prospective current are rated current ir, peak current ip, pre-arcing time tp, arcing time ta, total operating time tt= tp + ta, pre-arcing i²t (i²t)p, arcing i²t (i²t)a and total operating i²t (i²t)t= (i²t)p + (i²t)a. Figure 1 illustrates some of these parameters. The prospective current for a circuit is the maximum current that would be reached if the fuse did not operate.

The i²t or current-squared time rating is a commonly used fuse characteristic when operating current levels are much higher that the rated fuse current ir. The circuit time constant defines the ratio L/R, where L and R are the effective circuit inductance and resistance components in series with the fuse and energy source.

A fuse model is developed in Section 2 and model validation is undertaken in Section 3. Section 4 discusses the development of other DC power system component models for application to the analysis of over-current protection, and the paper is summarised in Section 5.

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Combination Wave Generator SPICE simulation.

In this article, we will delve into the implementation and analysis of a versatile Combination Wave Generator SPICE simulation template. This template forms the groundwork for a range of applications including Surge Generators, Line Impedance Stabilization Networks (LISN), motor control, and ripple current analysis. Hardware engineers can capitalize on this model to streamline project development efforts.While using PSpice for simulation, you can effortlessly apply the fundamental principles of the Combination Wave Generator SPICE simulation template to various other SPICE simulation software platforms.

A “Combination Wave Generator” finds its application in Electromagnetic Compatibility (EMC) tests, generating specific waveform voltage or current pulses. Its purpose is to assess electronic devices’ electrical resilience and responses to abrupt variations or transients within the electromagnetic environment. These generators replicate transient electrical disruptions or surges that might manifest in electronic circuits during situations like electrostatic discharges, switching transients, or line surges.

The Combination Wave Generator is an essential component of EMC compliance tests, ensuring that electronic devices can operate in realistic electromagnetic environments without sustaining damage or unforeseen behaviors.

Simplified SPICE Model of Combo Wave Generator.

The simplified model of the CWG consists of an High-Voltage source U, a charging resistor Rc, an energy storage capacitor Cc. This part of circuit is connected by a switch to 2 Pulse duration shaping resistors Rs, an impedance matching resistor Rm and a Rise time shaping indutor Lr, as in the picture below

typical values of this components are: Cc=7.76μF, Rs1=14.8 Ohm, Rm=1.05 Ohm, Lr=9.74μH, Rs2=23.3 Ohm. The peak voltage on Rs2 can be 1KV, 2KV,..6KV.

In the following schematic we set the high voltage with the initial condition of the CapacitorCc, for example for 6KV, we set 6300 in the PSpice IC field of the Cc component. We can adjust the time in U1 to make surge hit at 90/270 degree or whatever phase we want.

Calibration of Surge Generator.

The IEC/EN 61000-4-5 standars requires the following waveform of open-circuit voltage with no Coupling/Decoupling network (CDN) connected

This is the result of the simulation that shows a voltage waveform that fullfills requirementof IEC/EN 61000-4-5

Below the image of the waveform of short-circuit current with no CDN connected

and here again the simulated results:

Ipeak is about 1.5KA, T1 is 8uS and T2 is 20uS. The effective coupling impedance is 2Ohm. The simulated current waveform fulfills requirement of IEC/EN 61000-4-5 standards.

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Importing SUBCKT PSpice Netlist into TINA

This article aims to offer a thorough exploration of Importing SUBCKT PSpice Netlist into TINA, focusing specifically on their application through the SUBCKT subcircuit statement. While the foundational syntax for basic components like resistors, capacitors, and inductors remains consistent across both TINA and PSpice platforms, the complexity increases when working with more elaborate models. In the case of more intricate models, it’s possible that certain PSpice netlists could encompass formats that are incompatible with TINA.

The article addresses this challenge by offering a detailed, step-by-step guide on importing a PSpice netlist into TINA. The primary objective is to ensure seamless syntax compatibility, ultimately resulting in the creation of a TINA macromodel.

To provide practical insight, we will employ the schematic of a speech band amplifier from TINA Designsoft’s extensive circuit collection. Within this circuit, we will showcase the application of two opa345 operational amplifiers, offering a tangible and illustrative example for our exploration into the process of Importing SUBCKT PSpice Netlist into TINA.

In addition, another article that might interest you for importing PSPice models into TINA is this one

We want to replace the SPICE model of the opa345 with the following opa347 PSpice netlist, which includes the SUBCKT statement:

rename the .txt file as opa347.cir, then from the menu File, choose Import, PSpice Netlist (.CIR)

When you select the ‘opa347.cir’ file, the Netlist Editor window opens

Click on the ‘Compile’ icon to verify the compatibility of SPICE statements with TINA. If there are no compatibility issues, a ‘Successfully completed’ message appears:

Close the Netlist Editor window, and then select ‘New Macro Wizard…’ from the ‘Tools’ menu

The “New Macro Wizard” window will appear. Enter “opa347” as the name and uncheck the “Current circuit” option. Now, you can select the file “opa347.cir” using the directory window. Make sure to uncheck “Auto-generated.”

Click on the “Shape” ellipsis icon and choose a graphic symbol from the list. If there are no symbols that accurately represent our model, you can leave the check in the “Auto-generated” box:

Save the macro (.TSM file) for example in the Macrolib directory:

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From the Capture schematic to the PCB layout

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